1. Field of the Invention
The present invention relates to a voltage generating circuit, and more particularly, to a voltage generating circuit capable of supplying stable output voltage regardless of a change in external input voltage.
2. Description of the Related Art
In general, the internal voltage in a semiconductor memory device is being reduced. To permit this reduction, a voltage generating circuit is included in a semiconductor memory device to use an external voltage as an internal voltage.
An internal voltage generating circuit for use in a semiconductor memory array is provided a large electric current from a supply driver having an external power source at a point in time when consumption of a large electric current is needed, thereby reducing a change in internal voltage. However, as the level of external voltage in a semiconductor memory device decreases, a difference between the external voltage and internal voltage is lowered.
A reduction in a difference between external voltage and internal voltage results in a reduction in the capability of an internal voltage generating circuit to supply electric current. As a result, the level of the internal voltage decreases, which makes it difficult to design an internal voltage generating circuit capable of supplying a substantially stable output voltage.
If the size of a driver of the internal voltage generating circuit is increased to increase the electric current supply capability of the driver, excessive current may flow through the driver when external voltage increases suddenly and then the internal voltage may be larger than a desired value.
FIG. 1 is a view of a conventional voltage generating circuit 100. FIG. 2 is a circuit diagram of the voltage generating circuit of FIG. 1. FIGS. 3(a) and (b) are graphs illustrating the relationship between external voltage and gate source voltage in the voltage generating circuit 100, and between the external voltage and a driving electric current.
Referring to FIGS. 1 through 3(b), the conventional voltage generating circuit 100 includes a voltage comparing circuit 110 and an internal voltage control circuit 140.
The voltage comparing circuit 110 includes transistors MP0, MP1, MP2, MN0, MN1, MN2, MN3, MN4, MN5 and MN6, illustrated in FIG. 2.
The voltage comparing circuit 110 compares internal voltage VCCA with reference voltage VREF, and generates output voltage VOUT according to a difference therebetween. The internal voltage control circuit 140 is a PMOS transistor that receives the output voltage VOUT via a gate and supplies external voltage VCC to a load 150.
In the event that the current driving capability of the voltage generating circuit 100 is lowered or the internal voltage VCCA in the voltage generating circuit 100 is above or below a desired value, the voltage restoring capability of the voltage generating circuit 100 is proportional to the amount of an electric current flowing through the voltage generating circuit 100. However, preferably, excessive consumption in power of the voltage generating circuit 100 does not occur.
Therefore, in most cases, the voltage generating circuit 100 is designed such that a small amount of an electric current is normally output, but a large electric current is output for a short time if it is required to supply a large electric current to the load 150 or rapidly restore voltage to the original state.
As the voltage comparing circuit 110, a differential amplification circuit 120 is used. In FIG. 1, ENS denotes an activation signal that is activated when a large electric current or fast restoration of voltage is required. If the activation signal ENS is activated, the voltage comparing circuit 110 and the internal voltage control circuit 140 are actuated to maintain the internal voltage VCCA to a desired level.
If the internal voltage VCCA is lower than the reference voltage VREF, the voltage comparing circuit 110 generates the output voltage VOUT to turn on the internal voltage control circuit 140. Then, the external voltage VCC increases a driving current IDRV flowing through the internal voltage control circuit 140, and thus, the internal voltage VCCA can be maintained constantly.
More specifically, a large load current ICCA flows through the load 150, the voltage comparing circuit 110 turns on a gate of the internal voltage control circuit 140, i.e., the PMOS transistor, using an electric current ISRC of the differential amplification circuit 120. As a result, the internal voltage control circuit 140 increases the response speed of the driving current IDRV, thereby preventing a rapid reduction in the internal voltage VCCA.
If the load current ICCA consumed by the load 150 decreases below a predetermined level, the differential amplification circuit 120 operates normally to keep balance between the driving current IDRV and the load current ICCA.
At this time, when the activation signal ENS is activated excessively for a long time and the external voltage VCC is high, the internal voltage VCCA increases abnormally. On the other hand, if the activation signal ENS is activated for too short a time and the external voltage VCC is low, the internal voltage VCC is lowered. Thus, it is important to appropriately control the activation signal ENS. However, control of the activation signal ENS is not easy because there are many factors to account for, e.g., conditions, such as temperature.
Further, the electric current ISRC of the differential amplification circuit 120 is set to be very large so as to rapidly turn on or off a gate of the PMOS transistor 140. In general, the differential amplification circuit 120 is designed such that the electric current ISRC flows through the differential amplification circuit 120 for a relatively long time. This causes unnecessary power consumption in the differential amplification circuit 120.
A current source circuit 130 of the voltage comparing circuit 110 supplies a small amount of an electric current IDDD to reduce the driving current IDRV when the external voltage VCC is high, and supplies a large amount of the electric current IDDD to increase the driving current IDRV when the external voltage VCC is low. That is, the current source circuit 130 is to constantly maintain the amount of the driving current IDRV flowing through the PMOS transistor 140 for a desired time.
However, in fact, the amount of the driving current IDRV flowing through the PMOS transistor 140 is not perfectly constant for a desired time. That is, despite use of the current source circuit 130 in the voltage comparing circuit 110, the driving current IDRV is affected by variations in the external voltage VCC.
Recently, the external voltage VCC has been lowered to a range from 2.5 V to 1.8 V, and as a result, a difference between the external voltage VCC and the internal voltage VCCA is reduced to several hundred mV. In this case, even if a gate of the PMOS transistor 140 is rapidly turned on or off, the driving current IDRV is proportional to the external voltage VCC because the PMOS transistor 140 operates in a triode region. This is illustrated in the graphs (a) and (b) shown in FIG. 3.
In a large PMOS transistor 140, the internal voltage VCCA does not decrease much although the external voltage VCC is low, but overshooting occurs when the external voltage VCC is high. On the contrary, in a small PMOS transistor 140, overshooting rarely occurs even if the external voltage VCC is high, but the internal voltage VCCA decreases significantly when the external voltage VCC is low.
Accordingly, a driving current IDRV that is not affected by variations in the external voltage VCC would be beneficial since the load current ICCA consumed by the load 150 is regular irrespective of the external voltage VCC.